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introduction
Micro Bump
Fine Pitch Micro Bump (Cu/SnAg)
Process Capability
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Micro Bump
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01.
8inch and 12inch Available
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02.
Target Product
- Micro-LED
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03.
Micro Bump Development Status
- 10um Pitch Internally Qualified
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04.
Thick Cu Stack-up Material : Electroplated Cu/Ni/Au
- Cu for Rs Reduction
- Ni for Diffusion Barrier
- Au for Wire Bonding (Au and Cu Wire Bonding Available)
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Micro Bump Material
- Ni / Lead Free SnAg
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01.
Road Map
introduction
Higher Performance WLCSP
Fine Pitch Micro Bump (Cu/SnAg)
Features
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01.
HC Series (by Thick RDL and UBM)
- HCTM 1 (Single RDL)
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02.
Comparison of Jmax
- Typical WLP (x1)
- HCTM WLP (x3)
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01.
introduction
FOWLP
Features
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01.
More Thinner Package Profile (by TB/DB System)
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02.
Higher Reliability (by Full UBM Wetting)
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02.
Higher Current Carrying Capacity (by Thicker RDL & UBM)
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01.
Development
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6mm x 6mm size FOWLP Internally Qualified
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Target Product
- PMIC, RFIC
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01.
Package information
| Layer | Specification |
|---|---|
| PKG Size | 2.6x2.6mm ~ 6.0x6.0mm (Under-develop 10x10mm) |
| Chip Size | 1.73x0.97mm ~ 5.0x5.0mm (Under-develop 7x7mm) |
| Ball Pitch | ≥0.35mm |
| Mold Thickness | 0.30~0.55mm |
| Bump Structure | 2P2M (3P3M under-develop by 2022) |
Road Map
introduction
Flip Chip PKG
Features
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FCCSP
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01.
Flip Chip Chip Scale Package
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02.
Substrate
- 2~6 Layer Build-up Substrate
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03.
Package Size
- 3~15mm
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04.
BGA Pitch
- 0.3~0.8mm
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05.
Bump Type
- Lead-Free & Cu Pillar Bump
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06.
Capillary Underfill(CUF) & Molded Underfill(MUF) Available
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01.
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FCBGA
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01.
Flip Chip Ball Grid Array
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02.
Substrate
- 4~8 layer build-up substrate
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03.
Package Size
- 15~35mm
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04.
BGA Pitch
- 0.4~1.0mm
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05.
Bump Type
- Lead-Free & Cu Pillar Bump
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06.
Bare die & thermally enhanced version w/ heat spreader available
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01.
