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Here are the products of LB Semicon made with No.1 Technology.
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Wafer-level Packaging (WLCSP) is the technology of packaging and testing an integrated circuit while at the wafer level and then slicing it into chips to make the completed product, which differs from the conventional method of slicing the processed wafer first into individual chips and then packaging them. WLCSP is a true chip-scale packaging technology. Demand for WLCSP is increasing rapidly in the mobile market, due to the realization of a true chip-scale package with excellent electrical properties and price competitiveness. The WLCSP continues to expand its scope of application. LB Semicon currently provides various layers of WLCSP solutions ranging from two layers to six layers tailored to meet the needs of our customers.
PMIC
RF & BB SoC
Transceiver
AOC
Sensors
Gold bumped wafers are in general applied on packages such as COG (Chip on Glass), COF(Chip on Film), COP(Chip on Plastic), primarily for consumer products. This technology was developed as an alternative to the wire bonding technology. The gold bumped chip will be mounted on the package through the thermal compression method. As demand is increasing for thin and lightweight packages with high I/O and flexible interconnection, these gold bumped wafers will represent a suitable solution for such products as mobile devices.
COF and COG PKG for TV
Monitor
Notebook DDIC
Mobile
Tablet
Automotive DIC
solder bump is being applied on various flip chip packages such as COC, fcBGA and fcQFN. LB Semicon currently provides a Lead-free solder bump solution based on a fine pitch structure, and even for the products such as wafers designed for QFN purpose that are not suitable for flip chip packages because of the pad position. Flip chip packages can still be applied without changing their pad layout with the help of the RDL process.
fcBGA PKG for AP
SoC
PMIC
Graphics
As semiconductor devices are rapidly becoming more integrated and faster, chip’s I/O density is increasing at a rapid pace while the bump pitch is continuously decreasing. Cu pillar is a bumping technology, developed to meet such needs for fine pitches, and it can accomplish much finer pitch of 40um or smaller, compared to the 150um level that existing Solder bumping method could reach. Cu pillar is currently being applied to various packages and its application will be expanded even more because of its excellent thermal dissipation performance and electro-migration properties, compared to Solder bumping.
fcBGA and fcQFN PKG for RFIC
BB & AP Processor
Power Amplifiers
NAND Flash
WiFi Module
Au RDL is mostly used to reposition the layout of the I/O pad so that the product becomes suitable for the wire bonding package. Au RDL provides an excellent wire bond-ability and high reliability, and it accomplishes SIP by repositioning the layout of the I/O pad in a way that makes it possible to apply a stack die wire bonding more easily without the pad layout design changes of memory devices.
Mostly used for Multi stack Wire bonding PKG for Memory such as NAND Flash and DRAM
Available for all applications that need Au wire bonding
In the thick Cu process, a layer is formed directly on the fab passivation without additional lower polymer protective layers. Due to low resistance of copper, this process provides a higher current efficiency compared to the general aluminum wiring, and the thick copper layer could absorb a significant amount of stress during the bonding process to ensure a wider bonding process window, and the use of various wires such as Au, pure and Pd/Cu wires allowing a BOAC process in a stable manner without worrying about cracks. * BOAC : a layout technology called “Bond Over Active Circuit”
Wire bonding PKG for Power Management IC and Memory
COG is an abbreviation of Chip On Glass, and it is a bonding technology thatdirectly connects the driver IC with conductive bumps on the glass panel, and is applied to high resolution LCD and OLED products.
A process where protective tapes are bonded to the patterned surface to protect the circuit side of a wafer and prevent wafer broken when Wafer Grinding
A process where the backside of the wafer is polished with blade wheels to meet our customers’ needs for low profile and small form factor products
A process where each chip is laser etched with a unique identification code to trace each of them
A process of removing the low-K layer and metal layer, which are difficult-to- cut-materials, using a laser.
A process of cutting the tape mounted wafer into individual chips based on the prescribed chip size
A process where dust particles on wafer surfaces are eliminated using plasma
A process where surface damage is inspected after chipping
A process where the adhesive strength of UV tapes is weakened for a smooth pickup
A process where only good quality chips from wafers that went through a sawing process are selectively transferred to the trays
A process where chips transferred to trays are visually inspected
A process where the good quality chips transferred to chip carriers or trays are subject to the pass/fail discrimination in accordance with visual inspection standards
A process where the good quality chips that have gone through the final selection process are subject to a series of packing including vacuum packing, inner packing and outer packing
A process where protective tapes are bonded to the patterned surface to protect the circuit side of a wafer and prevent wafer broken when Wafer Grinding
A process where the backside of the wafer is polished with blade wheels to meet our customers’ needs for low profile and small form factor products
A process of applying a special film on the back of the wafer to protect the chip from external impact
A process where each chip is laser etched with a unique identification code to trace each of them
A process where frames and wafers are bonded together using tapes to facilitate a sawing process
A process of removing the low-K layer and metal layer, which are difficult-to- cut-materials, using a laser
A process of cutting the tape mounted wafer into individual chips based on the prescribed chip size
A process where surface damage is inspected after chipping
A process where the adhesive strength of UV tapes is weakened for a smooth pickup
A process where only good quality chips from wafers that went through a sawing process are selectively transferred to the reels
A process where the good quality chips transferred to chip carriers or trays are subject to the pass/fail discrimination in accordance with visual inspection standards
A process where the good quality chips that have gone through the final selection process are subject to a series of packing including vacuum packing, inner packing and outer packing
The EDS (Electrical Die Sorting) process conducted by LB Semicon is a process that checks whether the quality characteristics of individual chips have reached the target level. It is operated to improve the work efficiency of subsequent processes by sorting out good/defective chips, correcting problems in the design stage, and sorting out defective chips in advance. We classify the device type according to the purpose of the semiconductor chip and perform electrical performance and quality inspection of the chip using a dedicated tester suitable for each chip's characteristics. In this process, the Auto Wafer Prober can be used to automatically, safely and quickly test individual chips. The tests can be categorized into three types: temperature, speed, and operation tests. Temperature tests are applied and tested by conditions from low temperature (Cold, -40℃) to high temperature (Hot, 125℃) because they must be operated in various temperature environments when actual chips are used. Speed tests measure the operating speed of the products. the operating speed of the semiconductor itself is important, but the communication speed with peripheral devices is also important, so it is vital to test the speed in various environments that meet the specifications of the chip. Operation tests include DC, AC, and function tests, and each test verifies current or voltage, analog characteristics, and operational status of each chip.
Application | Vendor | Model |
Specification (Pin mux, Pattern mux) |
Remark |
---|---|---|---|---|
DDI | Advantest | T6372(ND2) | 437.5MHz | - |
T6373(ND3) | 437.5MHz | HSIF : 1.25GHz | ||
T6391(ND4C) | 800MHz | UHSIF : 1.35GHz ~ 2.0GHz(License) | ||
T6391S(ND4ST) | 800MHz | UHSIF : 2.0GHz ~ 3.25GHz(License) | ||
Yokogawa | TS670 | - | UVI : 2.0A | |
ST6730A | 375MHz | NSIO | ||
ST6731A | 1.25GHz | GSIO | ||
PMIC | Eagle | ETS-364B | 66MHz | - |
Advantest | T2000-IPS | 250MBps | - | |
T2000-IPS/EPP | 250Mbps/800Mbps/1Gbps | - | ||
T2000-IPS 52TH | 1Gbps | GPWGD | ||
CIS | Advantest | T2000-ISS/32 | 800Mbps | 1.2G Capture Module |
T2000-ISS/64P | 1Gbps | 4.8G Capture Module | ||
SOC | Teradyne | Ultra-FLEX | 1600Mbps | - |
We provide a process solution that allows a wafer level chip test while minimizing losses, for the cases where sorting issues are raised or Test Program Debugging needs to be retested for chips after the sawing process.