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WLCSP You can check all our products made with our world’s number 1 technology at a glance here.


Wafer-level Packaging (WLCSP) is the technology of packaging and testing an integrated circuit while at the wafer level and then slicing it into chips to make the completed product, which differs from the conventional method of slicing the processed wafer first into individual chips and then packaging them. WLCSP is a true chip-scale packaging technology.
Demand for WLCSP is increasing rapidly in the mobile market, due to the realization of a true chip-scale package with excellent electrical properties and price competitiveness. The WLCSP continues to expand its scope of application.
LB Semicon currently provides various layers of WLCSP solutions ranging from two layers to six layers tailored to meet the needs of our customers.
PMIC, DMB RF & BB SoC, Transceiver, AOC, Sensors..

Bumping process capability
8inch and 12inch available
WLCSP structural option
2P1M (Single RDL without UBM)
2P2M (Single RDL with UBM)
3P3M (Dual RDL)
Ball pitch : 0.3, 0.35, 0.4, 0.5mm
Ball height
Ball drop : > 0.15mm
Electroplated : < 0.11mm (Lead free, SnAg 1.8%)
Re-PSV material option
High temperature curable Polyimide
Low temperature curable Polyimide
Re-PSV thickness : 5 to 20um
Re-PSV opening diameter
Min. diameter : 25um
RDL thickness : 3 to 10um (20um under development)
RDL width / space (min) : 8/8um

Backend process capability
Back-grinding for wafer thinning (min) : >150um
Backside coating : available
Scribe lane for dicing (min) : 60um (Laser grooving available)
Die size (min) available for TnR : 0.5x0.5mm
Inspection : Post sawing AOI, 6side inspection @ TnR